1. Field of the Invention
The present invention relates to a path detection apparatus in a CDMA reception device and, more specifically, to a path detection apparatus capable of eliminating the misidentification of a path as soon as possible.
2. Description of the Prior Art
A well-known path detecting method for use with the CDMA reception device generates a delay profile, and detects N (N indicates a natural number determined by the number of fingers) paths having high reception levels in the delay profile as the paths to be rake-combined.
The delay profile shows the reception level with the lapse of time as shown in FIG. 12. The delay profile is generated as follows. The horizontal axis shown in FIG. 12 indicates time with a scale indicating ¼ chip. The vertical axis indicates a reception level (code correlation value). One chip refers to a basic unit time in which a received signal is despread.
A reception level at a timing E1 is measured by despreading a received signal using a spread code replica at the timing E1. The timing E1 is set to the timing of the resolution for one chip, for example, the timing of ¼ resolution.
After the measurement at the timing E1, the one resolution timing is shifted, and the reception level is measured for the shifted timing. That is, the reception levels of the timings E2, E3, E4, . . . in FIG. 12 are sequentially measured. The frequency L of the measurement is the value determined by the search window size when a delay profile is generated in the multi-path search range.
The delay profile is thus generated by the L measured reception levels and the spread code replica.
FIG. 13 shows the configuration of the apparatus for use with the above mentioned conventional path detecting method. As shown in FIG. 13, the path detection apparatus is configured by despreading means 12, spread code replica generation means 14, a storage unit 16, highest reception level detection means 22, path detection means 4–28 and path masking means 30.
For input into the despreading means 12, a high frequency signal received by an antenna 11 is down-converted by a high frequency reception circuit 13, and a received signal obtained by performing a A/D conversion by a A/D conversion circuit 15 on the down-converted signal is provided. The received signal is provided for a finger 17, and the finger 17 outputs a signal (demodulated signal) despread based on the paths to be rake-combined (described later). The demodulated signal is provided for a rake reception circuit 19 and rake-combined. The rake-combined signal is provided for the circuit which regenerates received data not shown in the attached drawings.
In the despreading means 12 for receiving the received signal, the reception levels of a delay profile are sequentially generated using the spread code replica provided by the spread code replica generation means 14. The sequentially generated reception levels of the delay profile are stored in the storage unit 16.
The highest reception level detection means 22 reads the delay profile stored in the storage unit 16, and detects a path having the highest reception level as a reference path using the delay profile (SC1 shown in FIG. 14).
The path masking means 30 performs a masking process on the paths within ±¾ chip from the path to be rake-combined (SC2 shown in FIG. 14).
The path detection means 4–28 sets the reference path detected by highest reception level means 22 as a path to be rake-combined (SC3 shown in FIG. 14).
If the paths to be rake-combined for respective fingers have not been detected before this process (N in SC4 shown in FIG. 14), the highest reception level detection means 22 defines as a new reference path the path having the highest reception level in the paths having the reception levels lower than the reception level of the current reference path, thereby returning control to the process in step SC2 (SC5 shown in FIG. 14).
The above mentioned processes in steps SC2 to SC5 are repeated until the paths to be rake-combined for respective fingers can be detected.
When the paths to be rake-combined for respective fingers are detected (Y in SC4 shown in FIG. 4), the process of detecting a path terminates.
The detected paths are rake-combined for respective fingers by the rake reception circuit 19 after the detection.
The above mentioned conventional path detecting method detects N (N indicates the number of fingers) paths from the highest reception level sequentially to lower reception levels in the generated delay profile as the paths to be rake-combined.
Therefore, if the delay profile is, for example, as shown in FIG. 15 (the horizontal axis shown in FIG. 15 indicates time with a scale indicating 5 chips, and 24 dots of reception levels measured by ¼ chip resolution in one chip, and the vertical axis indicates a reception level (code correlation value)), and the peaks of the reception levels of the paths to be correctly rake-combined are F1, F2, and F3. The peaks relating to the interference of noise and fading or relating to code correlation are F4 and F5. Additionally, the peak relating to the interference between the path of the peak F1 and the path of the peak F2 appears as F6. Under the condition, if the number N of the fingers is F6, then the peaks F1 to F6 are all detected as the paths to be rake-combined. Therefore, the paths of the peaks F4 to F6 which are not to be rake-combined are misconceived as the paths to be rake-combined, thereby lowering the reception characteristic.
The ±n (n indicates a natural number determined by the resolution when a delay profile is generated) paths from the path detected as the path to be rake-combined are masked. Therefore, although the paths are to be effectively rake-combined, they are excluded.
Japanese Patent Laid-Open No. 2000-115030 (first well-known reference) discloses a CDMA reception device for reducing the deterioration of the reception characteristic by avoiding frequent switch of path timings obtained in the above mentioned conventional path detecting method.
That is, as shown in FIG. 16, the high frequency signal received by the antenna 11 is down-converted by the high frequency reception circuit 13, the signal output from the high frequency reception circuit 13 is A/D converted by the A/D conversion circuit 15, and the A/D converted received signal is provided for a sliding correlator 60.
The sliding correlator 60 generates a delay profile. A delay profile power addition unit 62 performs the process of leveling the path fluctuation by the fading, etc. on the generated delay profile, and an arithmetic unit 64 multiplies the delay profile on which the leveling process has been performed by a weight function from a status weight unit 66. A correlation peak position detection unit 68 which receives the weighted delay profile detects a path timing. The detected path timing is provided for a rake path assignment unit 70. The rake path assignment unit 70 assigns a path position to the finger 17, and sets a weight function. The method of setting a weight function by the rake path assignment unit 70 is to increase a peak value in the current path assignment position.
The arithmetic unit 64, the status weight unit 66, the correlation peak position detection unit 68, and rake path assignment unit 70 are in a DSP 74, the program stored in control memory 72 is read by the program execution unit (not shown in the attached drawings) of the DSP 74, and the program is executed therein to perform the function.
The above mentioned settings of a weight function works such that a path assigned to the finger portion can be set at a higher level.
Therefore, although a state in which path timings frequently switch occurs, the switch can be avoided.
The method of detecting a path timing disclosed in the above mentioned first well-known reference is a method of detecting paths to be rake-combined for respective fingers from a generated delay profile in order from the highest reception level as shown in steps SD1 to SD4 shown in FIG. 22.
Therefore, the method of detecting a path timing disclosed in the above mentioned first well-known reference is the same as the above mentioned conventional path detecting method, and there is the above mentioned technological problem.
Japanese Patent Laid-Open No. 10-336072 (second well-known reference) discloses a technological means for solving the above mentioned problem.
The rake receiver disclosed by the second well-known reference is configured as shown in FIG. 18, and includes the despreading means 12, spread code replica generation means 14, a storage unit 16, highest reception level detection means 22 lowest reception level detection means 52, first multiplication means 54, second multiplication means 56, the path masking means 30, and path detection means 5–28.
A received signal A/D converted by the A/D conversion circuit 15 shown in FIG. 13 is provided as input into the despreading means 12 as shown in FIG. 13.
In the despreading means 12 which receives the received signal, the reception levels of the delay profile are sequentially generated using the spread code replica provided by the spread code replica generation means 14. The sequentially generated reception levels of the delay profile are stored in the storage unit 16.
The highest reception level detection means 22 reads the delay profile stored in the storage unit 16, and detects the highest reception level using the delay profile. The lowest reception level detection means 52 reads the delay profile stored in the storage unit 16, and detects the lowest reception level using the delay profile. The first multiplication means 54 computes a first threshold G1 by multiplying the highest reception level detected by the highest reception level detection means 22 by a first threshold coefficient. The second multiplication means 56 computes a second threshold G2 by multiplying the lowest reception level detected by the lowest reception level detection means 52 by a second threshold coefficient (SE1 shown in FIG. 19).
The highest reception level detection means 22 detects the highest reception level using the delay profile stored in the storage unit 16, and also detects a path having the detected highest reception level as a reference path (SE2 shown in FIG. 19).
The path detection means 5–28 determines whether or not the reception level of the reference path detected by the highest reception level detection means 22 is larger than the first threshold G1 output by the first multiplication means 54 and the second threshold G2 output by the second multiplication means 56, and detects the path as a path to be rake-combined when it is larger (Y in SE3 shown in FIG. 19).
The path masking means 30 masks the paths within ±¾ chip from the path defined as the path to be rake-combined (SE4 shown in FIG. 19).
The above mentioned reference path is detected as a path to be rake-combined (SE5 in FIG. 19)
If the paths to be rake-combined for respective fingers have not been detected before the above mentioned process (N in SE6 shown in FIG. 19), the path detection means 5–28 defines as a new reference path the path having the highest reception level in the reception levels lower than the level of the current reference path, thereby returning control to the process in step SE2 (SE7 shown in FIG. 19).
The above mentioned processes in steps SE3 to SE7 are repeated until the paths to be rake-combined for respective fingers can be detected.
When the paths to be rake-combined for respective fingers are detected (Y in SE6 shown in FIG. 19), the path detecting process terminates.
The detected paths for respective fingers are rake-combined after the detection by a rake reception circuit connected to the path detection means 5–28 (refer to 19 shown in FIG. 13).
The path detecting method described in the above mentioned second well-known reference performs on each reference path a masking process of excluding paths within ±¾ chip from the reference path. Therefore, only the paths having the reception levels exceeding the first threshold G1 and the second threshold G2 are detected as paths to be rake-combined as shown in FIG. 20. The horizontal axis shown in FIG. 20 indicates time, and the display is the same as that shown in FIG. 15. The vertical axis indicates a reception level (code correlation value).
Therefore, in the peaks of the reception levels, the paths having the peaks F1, F2, and F3 are detected as the paths to be rake-combined. However, it is possible to determine that the paths having the peaks F4, F5, and F6 in the peaks of the reception levels are not to be rake-combined.
Nevertheless, when a delay profile contains the paths to be rake-combined having reception levels between the reception levels H1 and H2 as shown in FIG. 21, the reception characteristic can be improved by rake-combining the paths having the reception levels H1 and H2 as the paths to be rake-combined. The horizontal axis shown in FIG. 21 indicates time with a scale indicating ¼ chip. The vertical axis indicates a reception level (code correlation value).
However, in the path detecting method described in the above mentioned second well-known reference, the highest reception level and the lowest reception level are detected as mentioned above, the first threshold G1 and the second threshold G2 are computed from these reception levels, it is determined whether or not the highest reception level, in the above mentioned example, the reception level H1, is larger than the first threshold G1 and the second threshold G2, and the path having the reception level H1 is determined to be a path to be rake-combined. However, since the paths within ±¾ chip from the path having the reception level H1 are masked (the shadowed portion shown in FIG. 21 refers to a masked portion), the reception level H2 which is the second highest level following the reception level H1 is removed from the levels of the paths to be rake-combined, thereby failing in improving the reception characteristic. That is, there is the problem that the reception characteristic is lowered than in the case in which the paths to be rake-combined includes both reception levels H1 and H2.
When the paths to be rake-combined (having the reception levels I2 and I3 or the reception level between the reception levels I2 and I3) exist in the timing close to the path to be rake-combined (reception level I1) in the delay profile as shown in FIG. 22, and interfere with one another, the path having the reception level I1 is detected as a path to be rake-combined in the path detecting method described in the second well-known reference. However, the paths having the reception levels I2 and I3 or the reception level between the reception levels I2 and I3 (the shadowed portion shown in FIG. 22 refers to the masked portion) are also excluded from the paths to be rake-combined in the above mentioned masking process, thereby inevitably lowering the reception characteristic. The horizontal axis shown in FIG. 22 indicates time with a scale indicating ¼ chip. The vertical axis indicates a reception level (code correlation value).